Exciting Career Opportunity for RTL Design Engineers | Bangalore

RTL Engineer in -ASIC Flows LINT CDC (Clark Domain Crossing) DRC rule checking & Synthesis using RTL compiler Develop micro-architecture and RTL implementation  Block level/ full chip integration and design. Experience on ASIC  At least 3+ years experience with design, verification and timing tools such as those from Synopsys/Cadence Hands-on with Lint, CDC, LEC and preferably Low Power check tools Some experience of AXI/AHB design in System Verilog and timing, performance & power optimizations Good understanding of design implementation flows and tools (Synthesis, STA, and DFT) Good knowledge of configuration tools and workflow tools: Clearcase/ClearQuest, etc. Desired Skills Knowledge of Networks on Chip Fabric, I/O protocols like SDCC/DDR/USB/UART/SPI etc. would be a plus Work with functional verification team to review test plans and coverage Ability to explain the designs and document their functionality once they are complete.  Scripting experience - Perl or Tcl  CPU and debugging experience Salary: Not Disclosed by Recruiter Industry: Semiconductors / Electronics Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design Role Category:Programming & Design Role:Database Architect/Designer Keyskills System Verilog Synthesis ASIC RTL Design CDC LINT DRC ASIC Flows Desired Candidate Profile Please refer to the Job description above Education- UG: B.Tech/B.E. - Any Specialization PG:M.Tech - Any Specialization Doctorate:Doctorate Not Required